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14th Asian Test Symposium (ATS'05)
An Effective Design for Hierarchical Test Generation Based on Strong Testability
Calcutta, India
December 18-December 21
ISBN: 0-7695-2481-8
Hideyuki Ichihara, Faculty of Information Sciences Hiroshima City University
Tomoo Inoue, Faculty of Information Sciences Hiroshima City University
Naoki Okamoto, Graduate School of Information Sciences Hiroshima City University
Toshinori Hosokawa, College of Industrial Technology Nihon University
Hideo Fujiwara, Nara Institute of Science and Technology
Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this paper, we study a test plan generation algorithm for hierarchical test based on strong testability. We propose a heuristic algorithm for finding a control forest requiring a small number of hold functions by improving an existing test plan generation algorithm based on strong testability. Experimental results show that the proposed algorithm is effective in reducing additional hold functions, i.e., reducing hardware overhead and delay penalty of datapaths.
Index Terms:
Hierarchical test generation, strong testability,datapath, test plan.
Citation:
Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara, "An Effective Design for Hierarchical Test Generation Based on Strong Testability," ats, pp.288-293, 14th Asian Test Symposium (ATS'05), 2005
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