Reduced pin count testing (RPCT) has proven to be an effective solution to reduce structural test costs in a manufacturing environment. Traditionally, RPCT has focused on stuck-at faults and IO loop-back tests. However, as circuit feature sizes shrink and new technology nodes employed, at-speed tests are becoming critical to assure low defect levels. In this paper, we extend the RPCT technique to allow application of atspeed test patterns using low cost testers that are seriously pin limited. Existing boundary scan cells are modified to facilitate the application of at-speed patterns thereby having minimal impact on the design and test area overhead.