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14th Asian Test Symposium (ATS'05)
Calcutta, India
December 18-December 21
ISBN: 0-7695-2481-8
Yervant Zorian, Virage Logic, USA
Juan-Antonio Carballo, IBM Corporation, USA
In addition to designing the functionality, today?s SOC necessitates designing for manufacturability, yield and reliability. Such requirements are fundamentally transforming the current SoC design methodology techniques for enhancing manufacturability, yield and reliability or "DFX" to include yield enhancement techniques, resolution enhancement techniques, new or restricted design rules, variability-aware design, and the addition of a special family of embedded IP blocks, called infrastructure IP blocks. The latter blocks are meant to ensure manufacturability of the SoC and to achieve adequate levels of yield and reliability. The infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This tutorial analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of the above DFX techniques. Then, it concentrates on several examples of each of these techniques.
Citation:
Yervant Zorian, Juan-Antonio Carballo, "T1: Design for Manufacturability," ats, pp.xxviii-xxix, 14th Asian Test Symposium (ATS'05), 2005
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