13th Asian Test Symposium (ATS'04) Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores Kenting, Taiwan November 15-November 17 ISBN: 0-7695-2235-1
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.63
This paper reports an efficient design of Test Pattern Generators (TPGs) for a chip having multiple cores. It is built around nonlinear Cellular Automata (CA) based Pseudo-Random Pattern Generator (PRPG). The modular and cascadable structure of proposed n-cell PRPG can be utilized to construct the (n = 1)-cell PRPG without sacrificing the pseudo-randomness quality. The efficiency of such a scalable PRPG structure is demonstrated in designing the on-chip TPGs for a VLSI chip implementing multiple cores.
Citation:
Sukanta Das, Biplab K. Sikdar, P Pal Chaudhuri, "Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores," ats, pp.331-334, 13th Asian Test Symposium (ATS'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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