Adding Testability to an Asynchronous Interconnect for GALS SoC

A
ATS
2004
13th Asian Test Symposium (ATS'04)
Abstract - Adding Testability to an Asynchronous Interconnect for GALS SoC

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13th Asian Test Symposium (ATS'04)

Kenting, Taiwan

November 15-November 17

ISBN: 0-7695-2235-1

	ASCII Text	x
	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards, "Adding Testability to an Asynchronous Interconnect for GALS SoC," Asian Test Symposium, pp. 20-23, 13th Asian Test Symposium (ATS'04), 2004.

	BibTex	x
	@article{ 10.1109/ATS.2004.20, author = {Aristides Efthymiou and John Bainbridge and Douglas A. Edwards}, title = {Adding Testability to an Asynchronous Interconnect for GALS SoC}, journal ={Asian Test Symposium}, volume = {0}, year = {2004}, issn = {1081-7735}, pages = {20-23}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2004.20}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Adding Testability to an Asynchronous Interconnect for GALS SoC SN - 1081-7735 SP20 EP23 A1 - Aristides Efthymiou, A1 - John Bainbridge, A1 - Douglas A. Edwards, PY - 2004 KW - null VL - 0 JA - Asian Test Symposium ER -

Aristides Efthymiou, University of Manchester

John Bainbridge, University of Manchester

Douglas A. Edwards, University of Manchester

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.20

Asynchronous circuits offer great potential for solving the interconnect problems faced by system-on-chip designers, but their adoption has been held back by a lack of methodology and support for fabrication testing of such circuits. This paper addresses this problem using a partial scan approach which achieves a test coverage of 99.5% on the CHAIN network-on-chip interconnect fabric which is used as an example. Test patterns are generated by a custom program automatically, given the topology of the interconnect. In comparison to standard, asynchronous, full-scan LSSD methods, area savings in the order of 50% are noted.

Citation:

Aristides Efthymiou, John Bainbridge, Douglas A. Edwards, "Adding Testability to an Asynchronous Interconnect for GALS SoC," ats, pp.20-23, 13th Asian Test Symposium (ATS'04), 2004

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