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12th Asian Test Symposium (ATS'03)
Xi?an, China
November 16-November 19
ISBN: 0-7695-1951-2
ASCII Text
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Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir, "Testability Improvement During High-Level Synthesis," Asian Test Symposium, pp. 505, 12th Asian Test Symposium (ATS'03), 2003.
 
 
BibTex
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@article{ 10.1109/ATS.2003.1250874,
author = {Saeed Safari and Hadi Esmaeilzadeh and Amir-Hossein Jahangir},
title = {Testability Improvement During High-Level Synthesis},
journal ={Asian Test Symposium},
volume = {0},
year = {2003},
issn = {1081-7735},
pages = {505},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250874},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Asian Test Symposium
TI - Testability Improvement During High-Level Synthesis
SN - 1081-7735
SP
EP
A1 - Saeed Safari,
A1 - Hadi Esmaeilzadeh,
A1 - Amir-Hossein Jahangir,
PY - 2003
KW - null
VL - 0
JA - Asian Test Symposium
ER -
 
Saeed Safari, Sharif University of Technology
Hadi Esmaeilzadeh, University of Tehran
Amir-Hossein Jahangir, Sharif University of Technology
Improving testability during the early stages of High-Level Synthesis (HLS) reduces test hardware overheads, test costs, design iterations, and also improves fault coverage [1]. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement.
Citation:
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir, "Testability Improvement During High-Level Synthesis," ats, pp.505, 12th Asian Test Symposium (ATS'03), 2003
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