loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
12th Asian Test Symposium (ATS'03)
A DFT Approach for Path Delay Faults in Interconnected Circuits
Xi?an, China
November 16-November 19
ISBN: 0-7695-1951-2
ASCII Text
x 
 
Irith Pomeranz, Sudhakar M. Reddy, "A DFT Approach for Path Delay Faults in Interconnected Circuits," Asian Test Symposium, pp. 72, 12th Asian Test Symposium (ATS'03), 2003.
 
 
BibTex
x
 
@article{ 10.1109/ATS.2003.1250786,
author = {Irith Pomeranz and Sudhakar M. Reddy},
title = {A DFT Approach for Path Delay Faults in Interconnected Circuits},
journal ={Asian Test Symposium},
volume = {0},
year = {2003},
issn = {1081-7735},
pages = {72},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250786},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - A DFT Approach for Path Delay Faults in Interconnected Circuits
SN - 1081-7735
SP
EP
A1 - Irith Pomeranz,
A1 - Sudhakar M. Reddy,
PY - 2003
KW - null
VL - 0
JA - Asian Test Symposium
ER -
 
Irith Pomeranz, Purdue University
Sudhakar M. Reddy, University of Iowa
We propose a new DFT approach for path delay faults in interconnected circuits. The proposed approach places multiplexers on the interface between two circuits in order to create new testable paths through the interconnection. The new testable paths allow us to increase the number of paths tested in each circuit. This approach does not require interconnected circuits to be isolated by test wrappers.
Citation:
Irith Pomeranz, Sudhakar M. Reddy, "A DFT Approach for Path Delay Faults in Interconnected Circuits," ats, pp.72, 12th Asian Test Symposium (ATS'03), 2003
Usage of this product signifies your acceptance of the Terms of Use.