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10th Asian Test Symposium (ATS'01)
Framework of Timed Trace Theoretic Verification Revisited
Kyoto, Japan
November 19-November 21
ISBN: 0-7695-1378-6
ASCII Text
x 
 
B. Zhou, T. Yoneda, C. Myers, "Framework of Timed Trace Theoretic Verification Revisited," Asian Test Symposium, pp. 437, 10th Asian Test Symposium (ATS'01), 2001.
 
 
BibTex
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@article{ 10.1109/ATS.2001.990323,
author = {B. Zhou and T. Yoneda and C. Myers},
title = {Framework of Timed Trace Theoretic Verification Revisited},
journal ={Asian Test Symposium},
volume = {0},
year = {2001},
isbn = {0-7695-1378-6},
pages = {437},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2001.990323},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - Framework of Timed Trace Theoretic Verification Revisited
SN - 0-7695-1378-6
SP
EP
A1 - B. Zhou,
A1 - T. Yoneda,
A1 - C. Myers,
PY - 2001
VL - 0
JA - Asian Test Symposium
ER -
 
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.
Citation:
B. Zhou, T. Yoneda, C. Myers, "Framework of Timed Trace Theoretic Verification Revisited," ats, pp.437, 10th Asian Test Symposium (ATS'01), 2001
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