10th Asian Test Symposium (ATS'01) IDDQ Sensing Technique for High Speed IDDQ Testing Kyoto, Japan November 19-November 21 ISBN: 0-7695-1378-6
In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.
Citation:
Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita, "IDDQ Sensing Technique for High Speed IDDQ Testing," ats, pp.111, 10th Asian Test Symposium (ATS'01), 2001 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||