Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits

A
ATS
1999
Eighth Asian Test Symposium (ATS'99)
Abstract - Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits

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Eighth Asian Test Symposium (ATS'99)

Shanghai, China

November 16-November 18

ISBN: 0-7695-0315-2

	ASCII Text	x
	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita, "Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits," Asian Test Symposium, pp. 141, Eighth Asian Test Symposium (ATS'99), 1999.

	BibTex	x
	@article{ 10.1109/ATS.1999.810742, author = {Yoshinobu Higami and Yuzo Takamatsu and Kewal K. Saluja and Kozo Kinoshita}, title = {Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits}, journal ={Asian Test Symposium}, volume = {0}, year = {1999}, issn = {1081-7735}, pages = {141}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810742}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits SN - 1081-7735 SP EP A1 - Yoshinobu Higami, A1 - Yuzo Takamatsu, A1 - Kewal K. Saluja, A1 - Kozo Kinoshita, PY - 1999 KW - fault simulation KW - IDDQ testing KW - sequential circuit KW - bridging fault VL - 0 JA - Asian Test Symposium ER -

Yoshinobu Higami, Ehime University

Yuzo Takamatsu, Ehime University

Kewal K. Saluja, University of Wisconsin

Kozo Kinoshita, Osaka University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810742

This paper presents fault simulation techniques for selecting a small number of IDDQ measurement vectors from a given test sequence while maintaining the original fault coverage. The proposed method covers a class of bridging faults and uses parallel fault simulation where ever possible. Experimental results are presented to demonstrate the effectiveness of the proposed method.

Index Terms:

fault simulation, IDDQ testing, sequential circuit, bridging fault

Citation:

Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita, "Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits," ats, pp.141, Eighth Asian Test Symposium (ATS'99), 1999

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