For test application, data path circuits are divided into subcircuits. At the inputs and outputs of every subcircuit, accumulators to generate patterns and to compact test responses are configured from the other available modules. Test registers are inserted only at positions where appropriate paths from and to accumulators do not exist. A small set of test configurations is chosen so that all the modules of the data path are tested and the hardware overhead is as low as possible. For each test configuration, we construct a test schedule with minimum test application time. The presented scheduling approach is based on loop folding and uses an integer linear programming formulation. The scheduling procedure always finds a schedule with maximum throughput, which reduces test application times significantly.