A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD

A
ATS
1999
Eighth Asian Test Symposium (ATS'99)
Abstract - A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD

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Eighth Asian Test Symposium (ATS'99)

Shanghai, China

November 16-November 18

ISBN: 0-7695-0315-2

	ASCII Text	x
	W. Feng, W.K. Huang, F.J. Meyer, F. Lombardi, "A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD," Asian Test Symposium, pp. 95, Eighth Asian Test Symposium (ATS'99), 1999.

	BibTex	x
	@article{ 10.1109/ATS.1999.810735, author = {W. Feng and W.K. Huang and F.J. Meyer and F. Lombardi}, title = {A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD}, journal ={Asian Test Symposium}, volume = {0}, year = {1999}, issn = {1081-7735}, pages = {95}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810735}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD SN - 1081-7735 SP EP A1 - W. Feng, A1 - W.K. Huang, A1 - F.J. Meyer, A1 - F. Lombardi, PY - 1999 VL - 0 JA - Asian Test Symposium ER -

W. Feng, Lucent Technologies

W.K. Huang, Fudan University

F.J. Meyer, Northeastern University

F. Lombardi, Northeastern University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810735

In this paper, a novel architecture for Built-In Self Test (BIST) and different designs for both the Control and Data test pattern generators (CTPG and DTPG) are proposed for interconnect testing using the IEEE standard 1149.1. A general and complete procedure to implement this architecture is also presented. For the DTPG design, the complementary counting sequence (as an example of a maximal independent test set) is used for fault detection. One of the main features of this design is its independence with respect to the type of cell in the chain. A novel design is proposed for the CTPG to avoid damage to the circuit as well as to guarantee 100% fault coverage with low hardware overhead and time complexity.

Citation:

W. Feng, W.K. Huang, F.J. Meyer, F. Lombardi, "A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD," ats, pp.95, Eighth Asian Test Symposium (ATS'99), 1999

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