Seventh Asian Test Symposium (ATS'98) Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation Singapore December 02-December 04 ISBN: 0-8186-8277-9
In this paper, we propose a method of diagnosing gate delay faults using delay fault simulation. In the method, suspected faults are deduced by fault simulation and backward path-tracing using diagnostic test-pairs with observed faulty responses. Also, by fault simulation using diagnostic test-pairs with fault-free responses, non-existent faults are deduced, and they are removed from the set of suspected faults. Finally, we present experimental results on the ISCAS'85 benchmark circuits. The experimental results show that by simple processes of backward path-tracing and fault simulation, this method achieves reasonable diagnostic resolutions in a short time.
Citation:
Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, "Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation," ats, pp.108, Seventh Asian Test Symposium (ATS'98), 1998 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||