Fifth Asian Test Symposium (ATS'96) Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults Hsinchu, TAIWAN November 20-November 22 ISBN: 0-8186-7478-4
This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intermediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.
Index Terms:
CMOS logic circuits; CMOS bridging faults detection; ATPG system; built-in intermediate voltage sensing; BIFEST system; PODEM-like process; PPSFP-based process; logic monitoring; fault coverage; greedy algorithm; gate threshold ranges; Byzantine General's Command Problem; fault modelling; fault simulation; feedback bridging faults; parallel pattern single fault propagation
Citation:
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai, "Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults," ats, pp.100, Fifth Asian Test Symposium (ATS'96), 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb