Testing of a parallel ternary multiplier using I/sup 2/L logic

A
ATS
1995
Fourth Asian Test Symposium (ATS'95)
Abstract - Testing of a parallel ternary multiplier using I/sup 2/L logic

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Fourth Asian Test Symposium (ATS'95)

Bangalore, India

November 23-November 24

ISBN: 0-8186-7129-7

	ASCII Text	x
	M. De, B.P. Sinha, "Testing of a parallel ternary multiplier using I/sup 2/L logic," Asian Test Symposium, pp. 387, Fourth Asian Test Symposium (ATS'95), 1995.

	BibTex	x
	@article{ 10.1109/ATS.1995.485365, author = {M. De and B.P. Sinha}, title = {Testing of a parallel ternary multiplier using I/sup 2/L logic}, journal ={Asian Test Symposium}, volume = {0}, year = {1995}, isbn = {0-8186-7129-7}, pages = {387}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485365}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Testing of a parallel ternary multiplier using I/sup 2/L logic SN - 0-8186-7129-7 SP EP A1 - M. De, A1 - B.P. Sinha, PY - 1995 KW - multivalued logic circuits; fault location; integrated injection logic; multiplying circuits; fault diagnosis; logic testing; logic design; design for testability; adders; digital arithmetic; parallel ternary multiplier; I/sup 2/L logic; generalized model; multivalued I/sup 2/L circuits; test sets; parallel multiplier; input balanced ternary full adder; precarry generator; multivalued current inputs; multivalued current outputs; generated test sets; stuck-at fault; skew fault; adder VL - 0 JA - Asian Test Symposium ER -

M. De, USIC, Kalyani Univ., West Bengal, India

B.P. Sinha, USIC, Kalyani Univ., West Bengal, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485365

A generalized model for faults in multivalued I/sup 2/L circuits has been proposed. Using this model, the test sets have been generated for testing the basic modules of a parallel multiplier using multivalued I/sup 2/L technology. These basic modules include four input balanced ternary full adder and a precarry generator, each of which has multivalued current inputs and outputs. The generated test sets can detect single faults (either 'stuck-at' or 'skew' type) in these circuits.

Index Terms:

multivalued logic circuits; fault location; integrated injection logic; multiplying circuits; fault diagnosis; logic testing; logic design; design for testability; adders; digital arithmetic; parallel ternary multiplier; I/sup 2/L logic; generalized model; multivalued I/sup 2/L circuits; test sets; parallel multiplier; input balanced ternary full adder; precarry generator; multivalued current inputs; multivalued current outputs; generated test sets; stuck-at fault; skew fault; adder

Citation:

M. De, B.P. Sinha, "Testing of a parallel ternary multiplier using I/sup 2/L logic," ats, pp.387, Fourth Asian Test Symposium (ATS'95), 1995

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