Fourth Asian Test Symposium (ATS'95) Deterministic test generation for non-classical faults on the gate level Bangalore, India November 23-November 24 ISBN: 0-8186-7129-7
This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault models: stuck-at faults, function conversions, bridging faults, transition faults and faults with additional fault detection conditions. CONTEST is part of a complete test generation system for non-classical faults which consists of a test pattern generator, a fault simulator and a fault list generator. The fault list generator uses a library-based fault modeling strategy which allows the specification of realistic target fault sets. Experimental results show that CONTEST can efficiently handle non-classical faults on the gate level. For a complex target fault set which encompasses for example stuck-at, stuck-open and bridging faults, a test efficiency of 100% has been achieved for each of the ISCAS benchmark circuits containing up to 38,000 nodes.
Index Terms:
combinational circuits; fault diagnosis; logic testing; logic CAD; design for testability; automatic test software; CMOS logic circuits; deterministic algorithms; deterministic test pattern generator; combinational circuits; CONTEST; gate level fault models; stuck-at faults; function conversions; bridging faults; transition faults; nonclassical faults; fault simulator; fault list generator; library-based fault modeling strategy; test efficiency; ISCAS benchmark circuits; algorithm; scan-based circuits; CMOS cell library; logic simulation; ATPG
Citation:
U. Mahlstedt, J. Alt, I. Hollenbeck, "Deterministic test generation for non-classical faults on the gate level," ats, pp.244, Fourth Asian Test Symposium (ATS'95), 1995 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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