Static compaction for two-pattern test sets

A
ATS
1995
Fourth Asian Test Symposium (ATS'95)
Abstract - Static compaction for two-pattern test sets

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	Similar Articles Articles by I. Pomeranz Articles by S.M. Reddy

Fourth Asian Test Symposium (ATS'95)

Bangalore, India

November 23-November 24

ISBN: 0-8186-7129-7

	ASCII Text	x
	I. Pomeranz, S.M. Reddy, "Static compaction for two-pattern test sets," Asian Test Symposium, pp. 222, Fourth Asian Test Symposium (ATS'95), 1995.

	BibTex	x
	@article{ 10.1109/ATS.1995.485340, author = {I. Pomeranz and S.M. Reddy}, title = {Static compaction for two-pattern test sets}, journal ={Asian Test Symposium}, volume = {0}, year = {1995}, isbn = {0-8186-7129-7}, pages = {222}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485340}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Static compaction for two-pattern test sets SN - 0-8186-7129-7 SP EP A1 - I. Pomeranz, A1 - S.M. Reddy, PY - 1995 KW - combinational circuits; logic testing; fault diagnosis; automatic testing; built-in self test; integrated circuit testing; delays; CMOS logic circuits; two-pattern test sets; static compaction procedure; test set size reduction; redundant tests removal; redundant patterns removal; fault coverage; delay faults; CMOS stuck open faults; ATPG; reordering of tests; digital logic circuits; combinational circuits VL - 0 JA - Asian Test Symposium ER -

I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485340

We propose a static compaction procedure to reduce the size of a test set comprised of two-pattern tests. The procedure reorders the tests in the test set to maximize the number of faults detected by adjacent patterns, thus allowing some of the tests to be dropped. In addition, the procedure removes redundant tests and redundant patterns, that can be omitted without reducing the fault coverage. Experimental results are presented to evaluate the effectiveness of the compaction procedure.

Index Terms:

combinational circuits; logic testing; fault diagnosis; automatic testing; built-in self test; integrated circuit testing; delays; CMOS logic circuits; two-pattern test sets; static compaction procedure; test set size reduction; redundant tests removal; redundant patterns removal; fault coverage; delay faults; CMOS stuck open faults; ATPG; reordering of tests; digital logic circuits; combinational circuits

Citation:

I. Pomeranz, S.M. Reddy, "Static compaction for two-pattern test sets," ats, pp.222, Fourth Asian Test Symposium (ATS'95), 1995

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