Tolerance DC bands of CMOS operational amplifier

A
ATS
1995
Fourth Asian Test Symposium (ATS'95)
Abstract - Tolerance DC bands of CMOS operational amplifier

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	Similar Articles Articles by H. Ihs Articles by C. Dufaza

Fourth Asian Test Symposium (ATS'95)

Bangalore, India

November 23-November 24

ISBN: 0-8186-7129-7

	ASCII Text	x
	H. Ihs, C. Dufaza, "Tolerance DC bands of CMOS operational amplifier," Asian Test Symposium, pp. 140, Fourth Asian Test Symposium (ATS'95), 1995.

	BibTex	x
	@article{ 10.1109/ATS.1995.485329, author = {H. Ihs and C. Dufaza}, title = {Tolerance DC bands of CMOS operational amplifier}, journal ={Asian Test Symposium}, volume = {0}, year = {1995}, isbn = {0-8186-7129-7}, pages = {140}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485329}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Tolerance DC bands of CMOS operational amplifier SN - 0-8186-7129-7 SP EP A1 - H. Ihs, A1 - C. Dufaza, PY - 1995 KW - CMOS analogue integrated circuits; operational amplifiers; circuit optimisation; fault diagnosis; integrated circuit testing; integrated circuit modelling; tolerance DC bands; CMOS operational amplifier; DC node voltages; data tolerance bands; foundry process fluctuations; DC branch current; OA; optimization; fault detection; design parameters; supply voltage; transistor size; fault simulation; fault model; catastrophic defects; transistor connections VL - 0 JA - Asian Test Symposium ER -

H. Ihs, Lab. d'Inf., de Robotique et de Micro-electron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

C. Dufaza, Lab. d'Inf., de Robotique et de Micro-electron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485329

This paper presents a test technique for CMOS operational amplifier based on the monitoring of some selected DC nodes' voltages and branches' currents. A realistic method for determining data tolerance bands due to the foundry process fluctuations of DC branches' currents and nodes' voltages of the OA is described. Optimization of the bounds for the fault detection problem is also possible by choosing carefully some design parameters like supply voltage or transistors' sizes. The efficiency of this technique has been proved by fault simulation when considering a fault model based on catastrophic defects of the transistors' connections.

Index Terms:

CMOS analogue integrated circuits; operational amplifiers; circuit optimisation; fault diagnosis; integrated circuit testing; integrated circuit modelling; tolerance DC bands; CMOS operational amplifier; DC node voltages; data tolerance bands; foundry process fluctuations; DC branch current; OA; optimization; fault detection; design parameters; supply voltage; transistor size; fault simulation; fault model; catastrophic defects; transistor connections

Citation:

H. Ihs, C. Dufaza, "Tolerance DC bands of CMOS operational amplifier," ats, pp.140, Fourth Asian Test Symposium (ATS'95), 1995

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