loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fourth Asian Test Symposium (ATS'95)
Fanout fault analysis for digital logic circuits
Bangalore, India
November 23-November 24
ISBN: 0-8186-7129-7
ASCII Text
x 
 
J.E. Chen, Chung Len Lee, Wen Zen Shen, Beyin Chen, "Fanout fault analysis for digital logic circuits," Asian Test Symposium, pp. 33, Fourth Asian Test Symposium (ATS'95), 1995.
 
 
BibTex
x
 
@article{ 10.1109/ATS.1995.485313,
author = {J.E. Chen and Chung Len Lee and Wen Zen Shen and Beyin Chen},
title = {Fanout fault analysis for digital logic circuits},
journal ={Asian Test Symposium},
volume = {0},
year = {1995},
isbn = {0-8186-7129-7},
pages = {33},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485313},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - Fanout fault analysis for digital logic circuits
SN - 0-8186-7129-7
SP
EP
A1 - J.E. Chen,
A1 - Chung Len Lee,
A1 - Wen Zen Shen,
A1 - Beyin Chen,
PY - 1995
KW - combinational circuits; fault diagnosis; logic testing; sequential circuits; fanout fault analysis; digital logic circuits; fault collapsing; combinational benchmark circuits; sequential benchmark circuits; target faults; test generation; fault simulation
VL - 0
JA - Asian Test Symposium
ER -
 
J.E. Chen, Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Chung Len Lee, Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Wen Zen Shen, Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Beyin Chen, Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2-8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.
Index Terms:
combinational circuits; fault diagnosis; logic testing; sequential circuits; fanout fault analysis; digital logic circuits; fault collapsing; combinational benchmark circuits; sequential benchmark circuits; target faults; test generation; fault simulation
Citation:
J.E. Chen, Chung Len Lee, Wen Zen Shen, Beyin Chen, "Fanout fault analysis for digital logic circuits," ats, pp.33, Fourth Asian Test Symposium (ATS'95), 1995
Usage of this product signifies your acceptance of the Terms of Use.