The recent evolution of semiconductor technology, in the last decades, brought tremendous improvements in performance increase at decreasing prices, perfectly following the famous Moore?s law. Lithography is still improving and allows 0.7X linear shrink per technology node. However, many products are hitting the "power wall"! Silicon is free, but peak power consumption, power density, heat dissipation are preventing a straight usage of the available silicon area. The simple shrink, even if it is a perfect way for cost reduction, does not support power density increase, and is not supported by packaging technology which does not scale as fast as silicon. On the other hand, scaling allows to double transistor count at each node at constant die size: then the challenge for tomorrow consists in improving performance while maintaining a reasonable power consumption. Architects and designers must improve MOPS/Watt. In the old times, VDD was scaled by 0.7, so there was enough room to increase both complexity and clock frequency.