This paper introduces an asynchronous radix-4 Booth multiplier architecture, which is scalable to arbitrary operand lengths while maintaining a constant cycle time per Booth iteration. Combined with the area effi- ciency of iterative multiplication, our multiplier architecture therefore is suitable for a range of emerging mobile applications, from handheld 3D graphics computation, which typically requires 32-bit multiplication, to cryptography, which can involve 1024-bit operands.

The multiplier architecture has several novel features, including: (i) a novel counterflow organization, in which the data bits flow in one direction and the Booth commands piggyback on the acknowledgments flowing in the opposite direction, (ii) overlapped execution of multiple iterations of the Booth algorithm, and (iii) design modularity and bitlevel pipelining, which enable the multiplier to be scaled to arbitrary operand widths without requiring gate resizing or cycle time overheads.

Spice simulations in a 0.18µm TSMC process at 1.8V, indicate promising performance: the multiplier takes 640-650ps per Booth iteration, regardless of the operand widths, thereby demonstrating the scalability of our approach. For 16-bit operands, this performance corresponds to nearly 200 Mega ops/sec throughput. Furthermore, the multiplier is fully functional at reduced supply voltages (e.g., 1.5V and 1.0V), and thus capable of dynamically trading off performance for energy efficiency.