We present the design of several so-called communication registers, which are modules that support non-blocking communication between two mutually asynchronous domains. For that purpose a communication register offers two mutually asynchronous access ports: a write and a read port. Communication registers differ from buffers in that read and write accesses are never held up. Consequently, data may get duplicated or lost. A read access, however, always delivers a value written into the register, although not necessarily the latest one.

Each of the two access ports is either clocked or self-timed, where the accesses through a self-timed port are controlled by handshakes. Therefore, one can distinguish four different kinds of modules: one for each possible access port combination. For all four cases we give simple designs, which in several cases are subsequently refined to meet additional requirements, such as setting an upper-bound to the mutual timing interference, keeping the power consumption low, or reducing the latency.