loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'05)
BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor
New York City, New York, USA
March 14-March 16
ISBN: 0-7695-2305-6
ASCII Text
x 
 
Virantha N. Ekanayake, Clinton Kelly, IV, Rajit Manohar, "BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor," Asynchronous Circuits and Systems, International Symposium on, pp. 144-154, 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/ASYNC.2005.14,
author = {Virantha N. Ekanayake and Clinton Kelly, IV and Rajit Manohar},
title = {BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor},
journal ={Asynchronous Circuits and Systems, International Symposium on},
volume = {0},
year = {2005},
issn = {1522-8681},
pages = {144-154},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2005.14},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asynchronous Circuits and Systems, International Symposium on
TI - BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor
SN - 1522-8681
SP144
EP154
A1 - Virantha N. Ekanayake,
A1 - Clinton Kelly, IV,
A1 - Rajit Manohar,
PY - 2005
KW - null
VL - 0
JA - Asynchronous Circuits and Systems, International Symposium on
ER -
 
Virantha N. Ekanayake, Cornell University
Clinton Kelly, IV, Cornell University
Rajit Manohar, Cornell University
We present a novel asynchronous processor architecture called BitSNAP that utilizes bit-serial datapaths with dynamic significance compression to yield extremely low-energy consumption. Based on the Sensor Network Asynchronous Processor (SNAP) ISA, BitSNAP can reduce datapath energy consumption by 50% over a comparable parallel-word processor, while still providing performance suited for powering low-energy sensor network nodes. In 180nm CMOS, the processor is expected to run at between 6 and 54 MIPS while consuming 152pJ/ins at 1.8V and just 17pJ/ins at 0.6V.
Citation:
Virantha N. Ekanayake, Clinton Kelly, IV, Rajit Manohar, "BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor," async, pp.144-154, 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.