The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new Asynchronous Network-On-Chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a Delay Insensitive asynchronous Network-on-Chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and Transaction-Level-Modeling. Preliminary simulation results show that the Asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13um CMOS technology.