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Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC'02)
An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz
Manchester, United Kingdom
April 08-April 11
ISBN: 0-7695-1540-1
Steven M. Nowick, Columbia University
Montek Singh, University of North Carolina at Chapel Hill
Sergey Rylov, IBM Thomas J. Watson Research Center
Alexander Rylyakov, IBM Thomas J. Watson Research Center
Jose A. Tierno, IBM Thomas J. Watson Research Center

A high-throughput low-latency digital finite impulse response (FIR) filter has been designed for use in partial-response maximum-likelihood (PRML) read channels of modern disk drives. The filter is a hybrid synchronous-asynchronous design. The speed-critical portion of the filter is designed as a high-performance asynchronous pipeline, sandwiched between synchronous input and output portions, making it possible for the entire filter to be dropped into a clocked environment. A novel feature of the filter is that the degree of pipelining is dynamically variable, depending upon the input data rate. This feature is critical in obtaining a very low filter latency throughout the range of operating frequencies.

The filter was fabricated in a 0.18 micron CMOS process. Resulting chips were fully functional over a wide range of supply voltages, and exhibited throughputs of over 1.3 Giga items/second, and latencies as low as four clock cycles. The internal asynchronous pipeline was estimated to be capable of significantly higher throughputs, around 1.8 Giga items/second. With these performance metrics, the filter has better performance than that reported for existing digital read channel filters.

Index Terms:
FIR filter, PRML read channel, magnetic recording, asynchronous pipeline, mixed timing, dynamic logic, high-throughput, low-latency, digital arithmetic, distributed arithmetic
Citation:
Steven M. Nowick, Montek Singh, Sergey Rylov, Alexander Rylyakov, Jose A. Tierno, "An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz," async, pp.84, Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC'02), 2002
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