Relative Timing

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Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)

Relative Timing

Barcelona, Spain

April 19-April 21

ISBN: 0-7695-0031-5

	ASCII Text	x
	Ken Stevens, Shai Rotem, Ran Ginosar, "Relative Timing," Asynchronous Circuits and Systems, International Symposium on, pp. 208, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASYNC.1999.761535, author = {Ken Stevens and Shai Rotem and Ran Ginosar}, title = {Relative Timing}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1999}, issn = {1522-8681}, pages = {208}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.1999.761535}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - Relative Timing SN - 1522-8681 SP EP A1 - Ken Stevens, A1 - Shai Rotem, A1 - Ran Ginosar, PY - 1999 VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

Ken Stevens, Intel Corporation

Shai Rotem, Intel Corporation

Ran Ginosar, Intel Corporation and Technion

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.1999.761535

Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits. Relative timing enables improved performance, area, power and testability in all three cases.

Citation:

Ken Stevens, Shai Rotem, Ran Ginosar, "Relative Timing," async, pp.208, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99), 1999

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