Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98) ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor San Diego, CA March 30-April 02 ISBN: 0-8186-8392-9
The design of a CMOS standard-cell Quasi-Delay-Insensitive (QDI) 16-bit asynchronous microprocessor is presented. ASPRO-216 is being developed for embedded applications. It is a scalar processor which issues instructions in-order and completes their execution out-of-order, and it can be customized both at the hardware and software levels to fit specific application requirements. Its architecture extensively uses an overlapping pipelined execution scheme involving de-synchronized units. The design flow and circuit style are an original application of A. Martin's method. The expected performance is 200 peak MIPS, 0.5 Watt using a 0.25 ?m technology.
Index Terms:
asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
Citation:
M. Renaudin, P. Vivet, F. Robin, "ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor," async, pp.0022, Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 1998 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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