Action Systems in Pipelined Processor Design

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	Similar Articles Articles by Juha Plosila Articles by Kaisa Sere

Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97)

Eindhoven, THE NETHERLANDS

April 07-April 10

ISBN: 0-8186-7922-0

	ASCII Text	x
	Juha Plosila, Kaisa Sere, "Action Systems in Pipelined Processor Design," Asynchronous Circuits and Systems, International Symposium on, pp. 156, Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997.

	BibTex	x
	@article{ 10.1109/ASYNC.1997.587171, author = {Juha Plosila and Kaisa Sere}, title = {Action Systems in Pipelined Processor Design}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1997}, isbn = {0-8186-7922-0}, pages = {156}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.1997.587171}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - Action Systems in Pipelined Processor Design SN - 0-8186-7922-0 SP EP A1 - Juha Plosila, A1 - Kaisa Sere, PY - 1997 KW - refinement calculus KW - pipelined processor design KW - action systems KW - asynchronous pipelined microprocessors KW - hazard situations KW - verifying refinement steps KW - circuit implementation KW - speed-independent techniques KW - refinement calculus VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

Juha Plosila, University of Turku, Department of Applied Physics, Finland

Kaisa Sere, Abe Akademi University, Department of Computer Science, Finland

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.1997.587171

We show that the action systems framework combined with the refinement calculus is a powerful method for handling a central problem in hardware design, the design of pipelines. We present a methodology for developing asynchronous pipelined microprocessors relying on this framework. Each functional unit of the processor is stepwise brought about which leads to a structured and modular design. The handling of different hazard situations is realized when verifying refinement steps. Our design is carried out with circuit implementation using speed-independent techniques in mind.

Index Terms:

refinement calculus, pipelined processor design, action systems, asynchronous pipelined microprocessors, hazard situations, verifying refinement steps, circuit implementation, speed-independent techniques, refinement calculus

Citation:

Juha Plosila, Kaisa Sere, "Action Systems in Pipelined Processor Design," async, pp.156, Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

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