2007 Asia and South Pacific Design Automation Conference
Fixing Design Errors with Counterexamples and Resynthesis
Yokohama
January 23-January 26
ISBN: 1-4244-0629-3
In this work we propose a new error-correction framework, called CoRe, which uses counterexamples, or bug traces, generated in verification to automatically correct errors in digital designs. CoRe is powered by two innovative resynthesis techniques, goal-directed search (GDS) and entropy-guided search (EGS), which modify the functionality of internal circuit's nodes to match the desired specification. We evaluate our solution to designs and errors arising during combinational equivalence-checking, as well as simulation-based verification of digital systems. Compared with previously proposed techniques, CoRe is more powerful in that: (1) it can fix a broader range of error types because it does not rely on specific error models; (2) it derives the correct functionality from simulation vectors, hence not requiring golden netlists; and (3) it can be applied to a range of verification flows, including formal and simulation-based.
Index Terms:
simulation-based verification, digital design errors, counterexamples, error-correction framework, digital designs, resynthesis techniques, goal-directed search, entropy-guided search, combinational equivalence-checking
Citation:
null Kai-Hui Chang, I.L. Markov, V. Bertacco, "Fixing Design Errors with Counterexamples and Resynthesis," asp-dac, pp.944-949, 2007 Asia and South Pacific Design Automation Conference, 2007