A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications

A
ASP-DAC
2007
2007 Asia and South Pacific Design Automation Conference
Abstract - A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications

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2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan, "A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications," Asia and South Pacific Design Automation Conference, pp. 908-913, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.358105, author = {Zhenyu Liu and Tughrul Arslan and Ahmet T. Erdogan}, title = {A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {908-913}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358105}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications SN - 1-4244-0629-3 SP908 EP913 A1 - Zhenyu Liu, A1 - Tughrul Arslan, A1 - Ahmet T. Erdogan, PY - 2007 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Zhenyu Liu, School of Engineering and Electronic, The University of Edinburgh, Edinburgh, EH9 3JL, UK. e-mail: z

Tughrul Arslan, School of Engineering and Electronic, The University of Edinburgh Edinburgh, EH9 3JL, UK. e-mail: T.

Ahmet T. Erdogan, School of Engineering and Electronic, The University of Edinburgh Edinburgh, EH9 3JL, UK. e-mail: Ah

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358105

The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low power consumption. Distributed Arithmetic (DA) is a powerful algorithm wildly used in many fields of multimedia for its efficiency. This paper presents a novel reconfigurable adder-based architecture for DA to realize the inner product which is the key computation in many digital signal processing applications. 1D DCT is mapped onto the architecture. Compared with some existing ASIC designs, the new architecture achieves good performance in area, speed and power.

Citation:

Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan, "A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications," asp-dac, pp.908-913, 2007 Asia and South Pacific Design Automation Conference, 2007

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