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2007 Asia and South Pacific Design Automation Conference
Design Methodology for 2.4GHz Dual-Core Microprocessor
Yokohama
January 23-January 26
ISBN: 1-4244-0629-3
ASCII Text
x 
 
Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda, "Design Methodology for 2.4GHz Dual-Core Microprocessor," Asia and South Pacific Design Automation Conference, pp. 896-901, 2007 Asia and South Pacific Design Automation Conference, 2007.
 
 
BibTex
x
 
@article{ 10.1109/ASPDAC.2007.358103,
author = {Noriyuki Ito and Hiroaki Komatsu and Akira Kanuma and Akihiro Yoshitake and Yoshiyasu Tanamura and Hiroyuki Sugiyama and Ryoichi Yamashita and Ken-ichi Nabeya and Hironobu Yoshino and Hitoshi Yamanaka and Masahiro Yanagida and Yoshitomo Ozeki and Kinya Ishizaka and Takeshi Kono and Yutaka Isoda},
title = {Design Methodology for 2.4GHz Dual-Core Microprocessor},
journal ={Asia and South Pacific Design Automation Conference},
volume = {0},
year = {2007},
isbn = {1-4244-0629-3},
pages = {896-901},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358103},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asia and South Pacific Design Automation Conference
TI - Design Methodology for 2.4GHz Dual-Core Microprocessor
SN - 1-4244-0629-3
SP896
EP901
A1 - Noriyuki Ito,
A1 - Hiroaki Komatsu,
A1 - Akira Kanuma,
A1 - Akihiro Yoshitake,
A1 - Yoshiyasu Tanamura,
A1 - Hiroyuki Sugiyama,
A1 - Ryoichi Yamashita,
A1 - Ken-ichi Nabeya,
A1 - Hironobu Yoshino,
A1 - Hitoshi Yamanaka,
A1 - Masahiro Yanagida,
A1 - Yoshitomo Ozeki,
A1 - Kinya Ishizaka,
A1 - Takeshi Kono,
A1 - Yutaka Isoda,
PY - 2007
KW - null
VL - 0
JA - Asia and South Pacific Design Automation Conference
ER -
 
Noriyuki Ito, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan. ito.noriyuki@jp.fujitsu
Hiroaki Komatsu, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Akira Kanuma, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Akihiro Yoshitake, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Yoshiyasu Tanamura, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Hiroyuki Sugiyama, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Ryoichi Yamashita, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Ken-ichi Nabeya, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Hironobu Yoshino, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Hitoshi Yamanaka, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Masahiro Yanagida, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Yoshitomo Ozeki, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Kinya Ishizaka, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Takeshi Kono, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Yutaka Isoda, Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64? microprocessor with 90nm CMOS technology. It focuses on the newly adopted techniques, such as efficient data management in dual-core design, fast delay calculation of the noise-immune clock distribution circuit, enhanced signal integrity analysis of a large-scale custom macro design, and enhanced diagnosis capability using a logic BIST circuit.
Citation:
Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda, "Design Methodology for 2.4GHz Dual-Core Microprocessor," asp-dac, pp.896-901, 2007 Asia and South Pacific Design Automation Conference, 2007
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