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2007 Asia and South Pacific Design Automation Conference
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time
Yokohama
January 23-January 26
ISBN: 1-4244-0629-3
J. Peddersen, Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW
S. Parameswaran, Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW
Numerous dynamic power management techniques have been proposed which utilize the knowledge of processor power/energy consumption at run-time. So far, no efficient method to provide run-time power/energy data has been presented. Current measurement systems draw too much power to be used in small embedded designs and existing performance counters can not provide sufficient information for run-time optimization. This paper presents a novel methodology to solve the problem of run-time power optimization by designing a processor that estimates its own power/energy consumption. Estimation is performed by the addition of small counters that tally events which consume power. This methodology has been applied to an existing processor resulting in an average power error of 2% and energy estimation error of 1.5%. The system adds little impact to the design, with only a 4.9% increase in chip area and a 3% increase in average power consumption. A case study of an application that utilizes the processor showcases the benefits the methodology enables in dynamic power optimization.
Index Terms:
dynamic power optimization, CLIPPER, counter-based low impact processor, run-time power optimization, power consumption, energy consumption
Citation:
J. Peddersen, S. Parameswaran, "CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time," asp-dac, pp.890-895, 2007 Asia and South Pacific Design Automation Conference, 2007
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