2007 Asia and South Pacific Design Automation Conference Design Consideration of 6.25 Gbps Signaling for High-Performance Server Yokohama January 23-January 26 ISBN: 1-4244-0629-3
As network data rate increases rapidly, high-speed signaling circuits for server communication pose many design challenges due to various system requirements using different interconnect mediums. This paper discusses main problems and solutions of high-speed circuits for server interconnect. Then, it presents a high-speed circuit implementation for such interconnect using 90nm CMOS technology that achieved data rate at 6.25 Gbps in a backplane environment.
Citation:
Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone, "Design Consideration of 6.25 Gbps Signaling for High-Performance Server," asp-dac, pp.854-857, 2007 Asia and South Pacific Design Automation Conference, 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||