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2007 Asia and South Pacific Design Automation Conference
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Yokohama
January 23-January 26
ISBN: 1-4244-0629-3
Chao-Hung Lu, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan, R.O.C. Email: ch
Hung-Ming Chen, E.E. Department and SoC Research Center, National Chiao Tung University, Hsinchu, Taiwan. Email: hmc
Chien-Nan Jimmy Liu, Department of Electrical Engineering, National Central University, Taoyuan, Taiwan, R.O.C. Email: ji
With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from over-design problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during early design stage in area-array designs. The experimental results are encouraging. Compared with other approaches in [15] and [12], we have inserted enough decap to meet supply noise constraint while others employ more area.
Citation:
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, "On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design," asp-dac, pp.792-797, 2007 Asia and South Pacific Design Automation Conference, 2007
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