2007 Asia and South Pacific Design Automation Conference Systematic Scan Reconfiguration Yokohama January 23-January 26 ISBN: 1-4244-0629-3
We present a new test data compression technique that achieves 10times to 40times compression ratios without requiring any information from the ATPG tool about the unspecified bits. The technique is applied to both single-stuck as well as transition fault test sets. The technique allows aggressive parallelization of scan chains leading to similar reduction in test time. It also reduces tester pins requirements by similar ratios. The technique is implemented using a hardware overhead of a few gates per scan chain.
Index Terms:
scan chains, systematic scan reconfiguration, test data compression technique, single-stuck fault test sets, transition fault test sets
Citation:
A.A. Al-Yamani, N. Devta-Prasanna, A. Gunda, "Systematic Scan Reconfiguration," asp-dac, pp.738-743, 2007 Asia and South Pacific Design Automation Conference, 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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