Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores

A
ASP-DAC
2007
2007 Asia and South Pacific Design Automation Conference
Abstract - Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores

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	Similar Articles Articles by Dan Zhao Articles by Unni Chandran Articles by Hideo Fujiwara

2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	Dan Zhao, Unni Chandran, Hideo Fujiwara, "Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores," Asia and South Pacific Design Automation Conference, pp. 714-719, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.358071, author = {Dan Zhao and Unni Chandran and Hideo Fujiwara}, title = {Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {714-719}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358071}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores SN - 1-4244-0629-3 SP714 EP719 A1 - Dan Zhao, A1 - Unni Chandran, A1 - Hideo Fujiwara, PY - 2007 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Dan Zhao, Center for Advanced Computer Studies, University at Louisiana, Lafayette, Lafayette, LA 70504-4330,

Unni Chandran, Center for Advanced Computer Studies, University at Louisiana, Lafayette, Lafayette, LA 70504-4330,

Hideo Fujiwara, Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma, Nara 630-01

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358071

This paper proposes a novel power-aware multi-frequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time and bandwidth are well handled by gating off certain virtual cores at a time while parallelizing the remaining. A shelf packing based optimization algorithm is proposed to design and optimize the wrapper architecture while minimizing the test time under power and bandwidth constraints.

Citation:

Dan Zhao, Unni Chandran, Hideo Fujiwara, "Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores," asp-dac, pp.714-719, 2007 Asia and South Pacific Design Automation Conference, 2007

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