A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs

A
ASP-DAC
2007
2007 Asia and South Pacific Design Automation Conference
Abstract - A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs

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2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	H. Hassan, M. Anis, M. Elmasry, "A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs," Asia and South Pacific Design Automation Conference, pp. 678-683, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.358065, author = {H. Hassan and M. Anis and M. Elmasry}, title = {A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {678-683}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358065}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs SN - 1-4244-0629-3 SP678 EP683 A1 - H. Hassan, A1 - M. Anis, A1 - M. Elmasry, PY - 2007 KW - 0.13 micron KW - timing-driven algorithm KW - MTCMOS FPGA KW - MTCMOS CAD methodology KW - subthreshold leakage power reduction KW - nanometer FPGA KW - circuit timing information KW - CMOS process VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

H. Hassan, Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.

M. Anis, Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.

M. Elmasry, Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358065

A timing-driven MTCMOS (T-MTCMOS) CAD methodology is proposed for subthreshold leakage power reduction in nanometer FPGAs. The methodology uses the circuit timing information to tune the performance penalty due to sleep transistors according to the path delays, achieving an average leakage reduction of 44.36 % when applied to FPGA benchmarks using a CMOS 0.13mum process. Moreover, the methodology is applied to several FPGA architectures and CMOS technologies.

Index Terms:

0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process

Citation:

H. Hassan, M. Anis, M. Elmasry, "A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs," asp-dac, pp.678-683, 2007 Asia and South Pacific Design Automation Conference, 2007

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