Runtime leakage power estimation technique for combinational circuits

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	Similar Articles Articles by null Yu-Shiang Lin Articles by D. Sylvester

2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	null Yu-Shiang Lin, D. Sylvester, "Runtime leakage power estimation technique for combinational circuits," Asia and South Pacific Design Automation Conference, pp. 660-665, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.358062, author = {null Yu-Shiang Lin and D. Sylvester}, title = {Runtime leakage power estimation technique for combinational circuits}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {660-665}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358062}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Runtime leakage power estimation technique for combinational circuits SN - 1-4244-0629-3 SP660 EP665 A1 - null Yu-Shiang Lin, A1 - D. Sylvester, PY - 2007 KW - subthreshold leakage analysis KW - runtime leakage power estimation technique KW - combinational circuits KW - dynamic estimation methods KW - static estimation methods KW - SPICE simulations KW - error estimation VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

null Yu-Shiang Lin, Electron. Eng.&Comput. Sci., Michigan Univ.

D. Sylvester, Electron. Eng.&Comput. Sci., Michigan Univ.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358062

This paper carefully examines subthreshold leakage during circuit operation (runtime) and develops a novel analysis technique to capture this important effect, which is currently ignored in traditional steady-state leakage calculation approaches. We implement novel dynamic and static estimation methods that provide significant speed improvements over full SPICE simulations and yield estimation errors of approximately 12% on average compared to more than 2times errors in steady-state based subthreshold leakage analysis.

Index Terms:

subthreshold leakage analysis, runtime leakage power estimation technique, combinational circuits, dynamic estimation methods, static estimation methods, SPICE simulations, error estimation

Citation:

null Yu-Shiang Lin, D. Sylvester, "Runtime leakage power estimation technique for combinational circuits," asp-dac, pp.660-665, 2007 Asia and South Pacific Design Automation Conference, 2007

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