Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits

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	Similar Articles Articles by null Youngsoo Shin Articles by null Sewan Heo Articles by null Hyung-Ock Kim Articles by null Jung Yun Choi

2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	null Youngsoo Shin, null Sewan Heo, null Hyung-Ock Kim, null Jung Yun Choi, "Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits," Asia and South Pacific Design Automation Conference, pp. 654-659, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.358061, author = {null Youngsoo Shin and null Sewan Heo and null Hyung-Ock Kim and null Jung Yun Choi}, title = {Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {654-659}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358061}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits SN - 1-4244-0629-3 SP654 EP659 A1 - null Youngsoo Shin, A1 - null Sewan Heo, A1 - null Hyung-Ock Kim, A1 - null Jung Yun Choi, PY - 2007 KW - 90 nm KW - subthreshold leakage current KW - gate leakage current KW - nanometer-scale CMOS circuits KW - power gating KW - supply switching KW - ground collapse KW - standard-cell elements KW - 45 nm KW - 65 nm VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

null Youngsoo Shin, Dept. of Electr. Eng., KAIST, Daejeon

null Sewan Heo, Dept. of Electr. Eng., KAIST, Daejeon

null Hyung-Ock Kim, Dept. of Electr. Eng., KAIST, Daejeon

null Jung Yun Choi

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358061

Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific to power gating, such as storage elements and output interface circuits with a data-retention capability. A new scheme called supply switching with ground collapse is proposed to control both gate and subthreshold leakage in nanometer-scale CMOS circuits. Compared to power gating, the leakage is cut by a factor of 6.3 with 65nm and 8.6 with 45nm technology. Various issues in implementing the proposed scheme using standard-cell elements are addressed, from RTL to layout. The proposed design flow is demonstrated on a commercial design with 90nm technology, and the leakage saving by a factor of 32 is observed with 3% and 6% of increase in area and wirelength, respectively.

Index Terms:

90 nm, subthreshold leakage current, gate leakage current, nanometer-scale CMOS circuits, power gating, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm

Citation:

null Youngsoo Shin, null Sewan Heo, null Hyung-Ock Kim, null Jung Yun Choi, "Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits," asp-dac, pp.654-659, 2007 Asia and South Pacific Design Automation Conference, 2007

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