So far, low power design for SoC has mainly focused on techniques to reduce dynamic power and standby leakage power. In further scaled devices, design technology to reduce active leakage power at the operation mode becomes indispensable. This is because the share of leakage power in the total operation power continues to increase as the device gets scaled. This paper gives a brief overview on the conventional leakage reduction techniques and describes novel approaches to use run-time power gating for active leakage reduction.