A High-Throughput Low-Power AES Cipher for Network Applications

A
ASP-DAC
2007
2007 Asia and South Pacific Design Automation Conference
Abstract - A High-Throughput Low-Power AES Cipher for Network Applications

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	Similar Articles Articles by null Shin-Yi Lin Articles by null Chih-Tsun Huang

2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	null Shin-Yi Lin, null Chih-Tsun Huang, "A High-Throughput Low-Power AES Cipher for Network Applications," Asia and South Pacific Design Automation Conference, pp. 595-600, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.358051, author = {null Shin-Yi Lin and null Chih-Tsun Huang}, title = {A High-Throughput Low-Power AES Cipher for Network Applications}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {595-600}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358051}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A High-Throughput Low-Power AES Cipher for Network Applications SN - 1-4244-0629-3 SP595 EP600 A1 - null Shin-Yi Lin, A1 - null Chih-Tsun Huang, PY - 2007 KW - 0.13 micron KW - low-power AES cipher KW - network applications KW - two-stage pipeline KW - CCM mode KW - design-for-test circuitry KW - CMOS technology KW - 4.27 Gbits/s KW - 333 MHz KW - 40.9 mW VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

null Shin-Yi Lin, Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu

null Chih-Tsun Huang

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358051

We propose a full-featured high-throughput low-power AES cipher which is suitable for widespread network applications. Different modes of operation are implemented, i.e., the ECB, CBC, CTR and CCM modes. Our cipher utilizes a cost-efficient two-stage pipeline for the CCM mode by a single datapath. With the design-for-test circuitry, the maximum throughput is 4.27 Gbps using a 0.13mum CMOS technology with a 333MHz clock rate. The hardware cost is 86.2K gates with the power of 40.9mW.

Index Terms:

0.13 micron, low-power AES cipher, network applications, two-stage pipeline, CCM mode, design-for-test circuitry, CMOS technology, 4.27 Gbits/s, 333 MHz, 40.9 mW

Citation:

null Shin-Yi Lin, null Chih-Tsun Huang, "A High-Throughput Low-Power AES Cipher for Network Applications," asp-dac, pp.595-600, 2007 Asia and South Pacific Design Automation Conference, 2007

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