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2007 Asia and South Pacific Design Automation Conference
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies
Yokohama
January 23-January 26
ISBN: 1-4244-0629-3
ASCII Text
x 
 
Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue, "Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies," Asia and South Pacific Design Automation Conference, pp. 565-570, 2007 Asia and South Pacific Design Automation Conference, 2007.
 
 
BibTex
x
 
@article{ 10.1109/ASPDAC.2007.358046,
author = {Zhangcai Huang and Hong Yu and Atsushi Kurokawa and Yasuaki Inoue},
title = {Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies},
journal ={Asia and South Pacific Design Automation Conference},
volume = {0},
year = {2007},
isbn = {1-4244-0629-3},
pages = {565-570},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358046},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asia and South Pacific Design Automation Conference
TI - Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies
SN - 1-4244-0629-3
SP565
EP570
A1 - Zhangcai Huang,
A1 - Hong Yu,
A1 - Atsushi Kurokawa,
A1 - Yasuaki Inoue,
PY - 2007
KW - null
VL - 0
JA - Asia and South Pacific Design Automation Conference
ER -
 
Zhangcai Huang, Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa
Hong Yu, Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa
Atsushi Kurokawa, Sanyo Semiconductor Co., Ltd, Gunma, 370-0596 Japan
Yasuaki Inoue, Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa
With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.
Citation:
Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue, "Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies," asp-dac, pp.565-570, 2007 Asia and South Pacific Design Automation Conference, 2007
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