2007 Asia and South Pacific Design Automation Conference Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection Yokohama January 23-January 26 ISBN: 1-4244-0629-3
This paper describes a new dynamic-power aware High Level Synthesis (HLS) data path approach that considers the close interrelation between clock choice and operations throughput selection whilst attempting to minimize area, power, or a combination thereoL It is shown that the proposed approach with its compound cost function and its novel clock and operations throughput selection algorithm, obtains solutions with lower power and area than using previous relevant work [11]. Moreover, different power-area tradeoffs can be explored due to the appropriate choice of clock period and operations throughput using our novel approach.
Citation:
M. A. Ochoa-Montiel, B. M. Al-Hashimi, P. Kollig, "Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection," asp-dac, pp.517-522, 2007 Asia and South Pacific Design Automation Conference, 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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