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2007 Asia and South Pacific Design Automation Conference
A Run-Time Memory Protection Methodology
Yokohama
January 23-January 26
ISBN: 1-4244-0629-3
Udaya Seshua, NXP Semiconductors, BL Personal, Millenia `D' Block, # 1, Murphy Road, Ulsoor 560008, Bangalore, Ind
Nagaraju Bussa, Philips Research, Philips Innovation Campus, # 1, Murphy Road, Ulsoor 560008, Bangalore, India. naga
Bart Vermeulen, NXP Semiconductors, Research, High Tech Campus 5, 5656 AE Eindhoven, The Netherlands. bart.vermeulen
In this paper we present a novel methodology to help debug memory corruption errors during application debug. In this methodology an optimal balance between hardware and software instrumentation is chosen to check at run-time all memory accesses made by an application. To achieve this balance a set of benchmark applications is first analyzed to determine their memory access patterns. The analysis results are used to make our approach low-cost both from a software performance penalty and a hardware area point-of-view. Experimental results show that our innovative approach typically requires less than 2% of a CPU in silicon area for a less than 1% run-time performance overhead. Our method is both low-cost and applicable to high performance microprocessors as well as time-constrained embedded systems.
Citation:
Udaya Seshua, Nagaraju Bussa, Bart Vermeulen, "A Run-Time Memory Protection Methodology," asp-dac, pp.498-503, 2007 Asia and South Pacific Design Automation Conference, 2007
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