Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM

A
ASP-DAC
2007
2007 Asia and South Pacific Design Automation Conference
Abstract - Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM

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	Similar Articles Articles by Jun-Fu Huang Articles by Victor C.Y. Chang Articles by Sally Liu Articles by Kelvin Y.Y. Doong Articles by Keh-Jeng Chang

2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	Jun-Fu Huang, Victor C.Y. Chang, Sally Liu, Kelvin Y.Y. Doong, Keh-Jeng Chang, "Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM," Asia and South Pacific Design Automation Conference, pp. 221-225, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.357989, author = {Jun-Fu Huang and Victor C.Y. Chang and Sally Liu and Kelvin Y.Y. Doong and Keh-Jeng Chang}, title = {Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {221-225}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357989}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM SN - 1-4244-0629-3 SP221 EP225 A1 - Jun-Fu Huang, A1 - Victor C.Y. Chang, A1 - Sally Liu, A1 - Kelvin Y.Y. Doong, A1 - Keh-Jeng Chang, PY - 2007 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Jun-Fu Huang, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.

Victor C.Y. Chang, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.

Sally Liu, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.

Kelvin Y.Y. Doong, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.

Keh-Jeng Chang, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357989

For sub-9Onm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/SoC design yields significantly. This paper presents a recent silicon test chip experiment result which uses a set of innovative nanometer test structures and Monte-Carlo-based three-dimensional electromagnetic RC simulations to achieve silicon-correlated corner modeling of OCV that can be applied to the upcoming statistics-based timing analysis (SSTA) for design for manufacturability (DFM). Modeling and correlating OCV based on the randomly varying physical process parameters is therefore achieved for the realistic corner modeling of advanced copper and low-K.

Citation:

Jun-Fu Huang, Victor C.Y. Chang, Sally Liu, Kelvin Y.Y. Doong, Keh-Jeng Chang, "Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM," asp-dac, pp.221-225, 2007 Asia and South Pacific Design Automation Conference, 2007

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