A Graph Reduction Approach to Symbolic Circuit Analysis

A
ASP-DAC
2007
2007 Asia and South Pacific Design Automation Conference
Abstract - A Graph Reduction Approach to Symbolic Circuit Analysis

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	Similar Articles Articles by null Guoyong Shi Articles by null Weiwei Chen Articles by C.J.-R. Shi

2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	null Guoyong Shi, null Weiwei Chen, C.J.-R. Shi, "A Graph Reduction Approach to Symbolic Circuit Analysis," Asia and South Pacific Design Automation Conference, pp. 197-202, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.357985, author = {null Guoyong Shi and null Weiwei Chen and C.J.-R. Shi}, title = {A Graph Reduction Approach to Symbolic Circuit Analysis}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {197-202}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357985}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A Graph Reduction Approach to Symbolic Circuit Analysis SN - 1-4244-0629-3 SP197 EP202 A1 - null Guoyong Shi, A1 - null Weiwei Chen, A1 - C.J.-R. Shi, PY - 2007 KW - symbolic analog circuit simulator KW - graph reduction KW - symbolic circuit analysis KW - binary decision diagram KW - recursive sign determination algorithm VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

null Guoyong Shi, Sch. of Microelectron., Shanghai Jiao Tong Univ.

null Weiwei Chen, Sch. of Microelectron., Shanghai Jiao Tong Univ.

C.J.-R. Shi

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357985

A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed graph reduction process and a recursive sign determination algorithm. A symbolic analog circuit simulator is developed using a combination of these techniques. The simulator is able to analyze large analog circuits in the frequency domain. Experimental results are reported.

Index Terms:

symbolic analog circuit simulator, graph reduction, symbolic circuit analysis, binary decision diagram, recursive sign determination algorithm

Citation:

null Guoyong Shi, null Weiwei Chen, C.J.-R. Shi, "A Graph Reduction Approach to Symbolic Circuit Analysis," asp-dac, pp.197-202, 2007 Asia and South Pacific Design Automation Conference, 2007

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