With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The Energyoptimal Sectioned Bus (ESB) template is an energy efficient architecture style for on-chip communication between components. To achieve minimum energy operation, the netlist topology of the ESB bus should however be optimized accordingly. In this paper we present a strategy for the definition of an energy optimal netlist for the ESB bus. An initial floorplanning stage provides information about the eventual lengths of the interconnect wires and a subsequent exploration step defines the optimal topology for the communication architecture. We motivate that a star topology generated using wire length prediction can be up to a factor 4 more energy efficient compared to standard linear bus topologies.