2007 Asia and South Pacific Design Automation Conference Low-Power High-Speed 180-nm CMOS Clock Drivers Yokohama January 23-January 26 ISBN: 1-4244-0629-3
The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were fabricated using 0.18-mum CMOS technology. The first and second stages of the driver consisted of a single inverter and m inverters, respectively, and the register array stage was constructed with N delay flip-flops (D-FFs). A single inverter in the second stage drove N/m D-FFs where N was fixed at 40 and m varied from 1 to 40. Minimum PT and tdT were 251 muW and 0.640 ns, respectively and were both obtained at an m of 8. These values were 48.6% and 29.4% of maximum PT and tdT respectively. Simulated and measured results agreed well with these SPICE simulated results.
Index Terms:
0.640 ns, CMOS clock drivers, power dissipation, delay time, register array, CMOS technology, delay flip-flops, 251 muW, 0.18 micron
Citation:
T. Enomoto, S. Nagayama, N. Kobayashi, "Low-Power High-Speed 180-nm CMOS Clock Drivers," asp-dac, pp.126-127, 2007 Asia and South Pacific Design Automation Conference, 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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