A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI

A
ASP-DAC
2007
2007 Asia and South Pacific Design Automation Conference
Abstract - A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI

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2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	M. Watanabe, F. Kobayashi, "A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI," Asia and South Pacific Design Automation Conference, pp. 124-125, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.357972, author = {M. Watanabe and F. Kobayashi}, title = {A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {124-125}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357972}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI SN - 1-4244-0629-3 SP124 EP125 A1 - M. Watanabe, A1 - F. Kobayashi, PY - 2007 KW - 0.35 micron KW - zero-overhead dynamic optically reconfigurable gate array VLSI KW - ZO-DORGA-VLSI KW - junction capacitance KW - photodiodes KW - load capacitance KW - configuration memory KW - CMOS process chip VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

M. Watanabe, Dept. of Syst. Innovation&Informatics, Kyushu Inst. of Technol., Fukuoka

F. Kobayashi, Dept. of Syst. Innovation&Informatics, Kyushu Inst. of Technol., Fukuoka

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357972

A zero-overhead dynamic optically reconfigurable gate array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 mum - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.

Index Terms:

0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip

Citation:

M. Watanabe, F. Kobayashi, "A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI," asp-dac, pp.124-125, 2007 Asia and South Pacific Design Automation Conference, 2007

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