A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology

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2007 Asia and South Pacific Design Automation Conference

Yokohama

January 23-January 26

ISBN: 1-4244-0629-3

	ASCII Text	x
	T. Kuboki, A. Tsuchiya, H. Onodera, "A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology," Asia and South Pacific Design Automation Conference, pp. 120-121, 2007 Asia and South Pacific Design Automation Conference, 2007.

	BibTex	x
	@article{ 10.1109/ASPDAC.2007.357970, author = {T. Kuboki and A. Tsuchiya and H. Onodera}, title = {A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {2007}, isbn = {1-4244-0629-3}, pages = {120-121}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357970}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology SN - 1-4244-0629-3 SP120 EP121 A1 - T. Kuboki, A1 - A. Tsuchiya, A1 - H. Onodera, PY - 2007 KW - 90 nm KW - on-chip signaling circuit KW - impedance-unmatched CML driver KW - CMOS technology KW - differential transmission-line KW - CML receiver KW - power reduction KW - CML buffer KW - load resistance tuning KW - 10 Gbit/s VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

T. Kuboki, Dept. of Commun.&Comput. Eng., Kyoto Univ.

A. Tsuchiya, Dept. of Commun.&Comput. Eng., Kyoto Univ.

H. Onodera, Dept. of Commun.&Comput. Eng., Kyoto Univ.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357970

An on-chip signaling system consists of a CML driver, a differential transmission-line and a CML receiver is fabricated. We developed an impedance-unmatched driver for power reduction. The impedance-unmatched driver reduces the tail current of the CML buffer by tuning the load resistance. The designed circuit achieves 3mm, 10Gbps/channel on-chip signal transmission and the impedance-unmatched driver saves the energy per bit by 21% compared with a conventional impedance-matched driver.

Index Terms:

90 nm, on-chip signaling circuit, impedance-unmatched CML driver, CMOS technology, differential transmission-line, CML receiver, power reduction, CML buffer, load resistance tuning, 10 Gbit/s

Citation:

T. Kuboki, A. Tsuchiya, H. Onodera, "A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology," asp-dac, pp.120-121, 2007 Asia and South Pacific Design Automation Conference, 2007

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